Data processing system and control method utilizing a plurality of date transfer means

ABSTRACT

The present invention provides a data processing system that includes a plurality of processing units and first, second, and third data transfer means. The first data transfer means connects a plurality of processing units in a network, exchanges first data, and configures at least one reconfigurable data flow by connecting at least two of the plurality of processing units. The second data transfer means supplies control information that loads setting data as second data to the plurality of processing units in parallel. The third data transfer means supplies the setting data to each of the plurality of the processing units individually. Setting data is data for setting a data flow with a different function by directly or indirectly changing other processing unit connected to a processing unit via the first data transfer means, and/or changing a process included in the processing unit.

TECHNICAL FIELD

The present invention relates to a data processing system that formsdata flows by connecting a plurality of processing units.

RELATED ART

U.S. Pat. No. 6,108,760 describes an art of connecting a plurality ofprocessing elements on a network and performing processing. However,when setting new functions in the processing elements, it is necessaryto supply data to the processing elements via the network, so that it isnecessary to temporarily free up the data path or data flow that isformed by the processing elements and so make it possible for thenetwork to supply the processing elements with the data required for thesettings. This means that it takes time to supply data for settings fromthe outside to the processing elements and configure a data path withdifferent functions. During such period, it is not possible to form adata flow and the elements become idle, which lowers the processingspeed. In order to configure data paths with different functions in ashort time, it is necessary to store all of the setting data beforehandinside the processing elements. It requires an extremely large memorycapacity per each of the processing elements, which makes this anunrealistic solution.

In U.S. Pat. No. 6,108,760, both physical identification numbers andvirtual identification numbers are assigned to each processing element,groups of arbitrary shapes, which are decided by the physical locationsof the processing elements for realizing certain functions, are definedby masking a part of identification numbers of either type, and settingdata and/or control data is/are supplied in units of groups. However,when the data flows are reconfigured, there is a high probability ofsignificant changes in the shapes that include processing elements thatrealize the different functions. Accordingly, if each processing elementis assigned a separate identification number so that the shapescorresponding to different functions can be expressed by masking somepart of the identification numbers, such identification numbers becomeso redundant, with it taking a great amount of time to look up and usesuch identification numbers during programming. This increases costs andalso reduces the flexibility of the system.

A method that supplies data to processing elements that are included ingroups of arbitrary shapes that are determined according to the physicalpositions can reduce the time taken in cases where the same setting datais supplied to a plurality of processing elements that are arranged inconcentrated groups. However, when the functions of the individualprocessing elements are different, it is ultimately necessary to supplysetting data separately to the individual processing elements orprocessing units that compose the data flow, which makes it impossibleto load setting data from the outside in a short time. This method istherefore incapable of achieving the fundamental aim of improving theprocessing speed.

In order to supply setting data separately to each processing elementvia a network, it must be possible to identify the respective processingelements. It is therefore necessary to assign separate identificationnumbers to each of the respective processing elements. To form groups ofarbitrary shapes using such independent identification numbers, acomplex system of identification numbers is required, with the controlmethod and hardware for recognizing such identification numbers alsobeing complex. This makes this solution uneconomical and makes itdifficult to raise the processing speed.

It is an object of the present invention to provide a data processingsystem in which a plurality of processing elements or processing unitsare connected via a network, where setting data is supplied to eachprocessing element and data paths and/or data flows with differentfunctions can be set dynamically and/or in clock cycle units. It is afurther object to provide a data processing system with a high degree ofprogramming freedom, in which the processing units are appropriatelyidentified for supplying setting data and/or control information simplywithout requiring complex processing, such as processing that assigns acomplex system of virtual addresses to processing units and masks thesystem for use.

DISCLOSURE OF THE INVENTION

The present invention provides a data processing system that includes aplurality of processing units and a first, second, and third datatransfer means. The first data transfer means connects the plurality ofprocessing units in a network, exchanges first data, and configures atleast one reconfigurable data flow by connecting at least two of theplurality of processing units. The second data transfer means suppliessecond data in parallel to the plurality of processing units. The thirddata transfer means supplies setting data to each of the plurality ofthe processing units individually. This setting data is data for settinga data flow with a different function by directly or indirectly changingother processing unit that is connected to a processing unit via thefirst data transfer means, and/or changing a processing included in theprocessing unit.

With this data processing system, setting data can be provided not bythe network-like first data transfer means or the second data transfermeans that broadcasts data but by the third data transfer means which isa dedicated bus that can supply data to each of the plurality ofprocessing units separately. Accordingly, since there is no need tospecify the address of each processing unit and to transfer the settingdata in order, setting data can be provided to a plurality of processingunits in a short time, such as one clock cycle. In addition, since thereis no need to assign the address to each of the processing units whendistributing setting data, virtual addresses and masking the address,which is troublesome processes, are unnecessary. The processing unitsthat belong to a data flow can be indicated by identificationinformation that simply shows the data flow.

The data flows in the present invention can be expressed as “functions”that are realized by taking over some or all of the processing units(hereinafter also referred to as “devices” and “elements”) that can beconnected by the first data transfer means that forms a network. Data isexchanged or distributed and processed within this function, with databeing received from and outputted to outside the network at the ends ofthe function. The data flow is autonomously or heteronomouslycontrolled, if there is a blockage on the data output side, for example,control is performed to temporarily halt the entire operation. As ageneral rule, data flows function independently, and internalinformation on the data flows is not actively exchanged between dataflows.

When controlling the data processing apparatus or system of the presentinvention, a first process that supplies, via the third data transfermeans, setting data and identification information showing the data flowto be set by the setting data, can attach the identification informationthat identifies the data flow to the processing units that configure thedata flow identified by the identification information. Then in thesecond process, by supplying the identification information with thesecond data via the second data transfer means, a process is performedfor selecting the second data based on the identification informationthat is supplied via the third data transfer means or the identificationinformation that has previously been supplied. This makes it possiblefor a plurality of processing units to select the second data in unitsof data flows and to perform processing according to such second data.Accordingly, it is preferable for the processing units to include meansfor selecting and processing the second data based on identificationinformation supplied via the third data transfer means.

The identification information that is used for selecting the seconddata can also be the identification information that is supplied by thethird data transfer means at the timing at which the second data issupplied. In this case, as one example the setting data to be loaded inthe processing units can be selected according to the identificationinformation that is supplied together with the setting data, that is theidentification information of the next data flow to which processingunits belong.

In the second process, it is possible to select the second data based onthe identification information supplied by the third data transfermeans. In order to store the supplied identification information, it ispreferable to provide the processing units with means, like a memory,for storing the identification information. In this case, setting datathat to be loaded into the processing unit can be selected by theidentification information that is stored in the processing unittogether with the previous setting data, which is the identificationinformation of the data flow to which the processing units presentlybelong.

According to the present invention, the most important content orcontext of the second data is control information (commands) thatcontrols operation of the processing unit. In particular, by supplying,via the second data transfer means, a first command for loading settingdata, it is possible for a plurality of sets of setting data to be setsynchronously in at least part of the plurality of the processing unitsrespectively using the identification information of the data flow to beconfigured by the sets of setting data. By doing so, the processingunits become identify the data flows to which they belong from theidentification information and thereafter can operate based on controlinformation that is appended with identification information. Theidentification information does not need to be information that canspecify each processing unit separately and may be simple informationthat is sufficient for identifying a data flow, which makes it possibleto identify a large number of data flows with little data.

Also, by supplying, via the second data transfer means, controlinformation for loading a set of setting data, the plurality of sets ofsetting data can be used by each of the plurality of processing unitssynchronously for configuring the data flows or functions and switchedthem instantaneously. Accordingly, new setting data can be dynamicallyloaded by the processing units that configure one particular data flowor data flows, then a new data flow or flows are configured.

A program or program product that controls the data processing system ofthe present invention includes instructions for executing processingthat supply, via the third transfer means, setting data andidentification information that shows the data flow to be set by thesetting data and supply, via the second transfer means, controlinformation for loading the setting data, with at least one ofidentification information. This program or program product can beprovided by recording the program or program product on a suitablerecording medium, and can alternatively be provided via a communicationmeans such as a computer network.

The setting data includes a variety of information for configuring adata flow. For example, if the first data transfer means is a networkthat transfers the first data by indicating the address(es) of theprocessing unit(s) that is/are connected, the setting data includes theaddress(es) of the processing unit(s) to be connected. Alternatively, ifthe processing units to be connected are indicated by selecting and/orswitching the wiring that composes the first data transfer means, thesetting data includes selection or connection information for thewiring. In addition, if the processing units are capable of changingtheir own processing contents, the setting data includes information forchanging process included in each of processing units for establishing adata path. Programmable processors are examples of processing units thatare capable of changing their own processing contents. The processingunits may also include a plurality of selectable internal data paths,with it being possible to select these internal data paths according tothe setting data.

While a general-purpose processor is capable of flexible processing,there is a tradeoff between flexibility and processing speed and highcosts are involved when improving the processing speed. On the otherhand, a processing unit that includes a plurality of internal data pathsis compact and inexpensive, is capable of high-speed processing, andstill has a certain degree of flexibility. Accordingly, by arranging aplurality of processing units with different types of internal datapaths and connecting these processing units with the first data transfermeans in the form of a network, it is possible to construct a dataprocessing system that is capable of performing a variety of processesat high speed. In addition, by using the present invention, theconfiguration of a data path or function can be changed dynamically.

In this data processing system of the present invention, the second datathat is supplied with the identification information via the second datatransfer means may be any data so long as it provides the data thatneeds to be supplied to a plurality of processing units with indicatinga specified data flow. An important data as the second data is controlinformation that controls the operations of the processing units, withone example of such information being a first command for loadingsetting data. Also, by supplying control information that has beenappended with identification information showing a data flow via thesecond data transfer means, a plurality of processing units can becontrolled in units of data flows. It is preferable for the dataprocessing system to supply control information for controlling theoperations of processing units with identification information thatindicates data flows via the second data transfer means. Also, it ispreferable for processing unit to include means for operating based onthe control information with identification information to that theprocessing unit belongs. In the same way, it is preferable for a controlmethod for the data processing system to include a process where, afteridentification information that shows a data flow and controlinformation that controls the operation of the processing unit have beensupplied via the second data transfer means, the processing unit operatebased on control information with identification information that eachof the processing units belongs to. In addition, it is preferable forthe program (program product) that controls this data processing systemto include instructions for executing process that supply, via thesecond data transfer means, control information, such as controlcommands, and identification information showing at least one data flow.

By supplying control information in parallel to a plurality ofprocessing units, which are connected in a network and form a data flowor data path that has a function for performing processing for apredetermined operation, the data flow configured by these processingunits can be precisely controlled in one clock cycle, for example, evenwhen the plurality of processing units are dispersed. Accordingly, it iseasy to synchronize and control a plurality of processing units thatcompose a data flow or to have a control processor perform suchcentralized control. As described above, the information that identifythe data flows do not need to be information that identify each of theprocessing units, which makes the information simple and means that lesshardware is required for processing. Accordingly, a data processingsystem with a high processing speed can be economically realized, andprocessing that switches between the plurality of functions that areprovided in the processing units in one clock cycle to configure a dataflow for a different function can be realized easily.

The control information is not limited to a command (the first command)for loading setting data, and includes a start command or a freeze orstop command (second command) that indicates a starting or stopping ofthe processing unit. It is possible to have the setting data loaded by astart command. By supplying a freeze command that indicates a stoppingof the processing unit via the second data transfer means together withidentification information, it is possible to synchronize and stop theprocessing of the processing units that compose the data flow(s)identified by the identification information. When it is necessary tostart the processing of a data flow for a different function withoutwaiting for the processing of presently constructed data flows to endand there are insufficient processing units, such control information iseffective for freeing up processing units and reconfiguring data flows.

In addition, it is also effective to supply, as control information, astore command (third command) for storing a state when the operation ofprocessing unit is stopped in a memory, and a load command (fourthcommand) for loading a state stored in the memory before the operationof the processing unit commences. When the processing of thereconstructed data flow(s) has ended and the original data flow(s)has/have been constructed, the stopped state is recreated. This meansthat the data processing system can operate reliably even when dataflows are dynamically reconstructed using a limited number of processingunits.

To make the processing units able to perform suitable processing forsuch commands and control information, it is preferable for theprocessing units to include means for loading setting data according tothe second data, means for starting or stopping operations according tothe second data, and saving means for stopping operations according tothe second data and also storing internal information on that processingunit in a memory and for loading internal information stored in thememory and commencing the operations. These means are realized by logiccircuits or microprograms or the like. Also, by storing the states ofthe processing units in the memory together with the identificationinformation, the control information that starts the operation can beselected based on the identification information stored in the memoryand data flows can be reconfigured.

The processing units referred to here may be remotely located. In thiskind of data processing system, the processing units use a computernetwork such as the Internet as the first data transfer means, a meansfor broadcasting wirelessly or via wires as the second data transfermeans, and a means that is capable of individual communications, such asa telephone network, as the third data transfer means. On the otherhand, it is also possible to arrange the processing units on a circuitboard such as a semiconductor substrate and so provide as a singleprocessor. In this case, the first data transfer means is networkcircuitry that connects the plurality of processing units, the seconddata transfer means is a circuit that connects the plurality ofprocessing units to a source or supplier of the second data, and thethird data transfer means is a circuit that connects the plurality ofprocessing units and a storage means that stores sets of setting datarespectively correspondingly to each of the processing units. Whencontrol information is supplied as the second data, the supplier servesas a control apparatus.

A number of methods are applicable for supplying different setting datato the processing units via the third data transfer means. As a firstmethod, a network setting memory capable of storing a plurality of setsof setting data for each of the plurality of processing units isprovided, and in a first process of the control method, according tocontrol by the control apparatus, a set of setting data that is to beset synchronously with at least part of the plurality of processingunits is selected and supplied out of the plurality of sets of settingdata stored in the network setting memory, then a command for loading issupplied in the second process. The amount of setting data that issupplied via the third data transfer means can be limited to theselected data sets, so that a narrow bus width is sufficient for thethird data transfer means, though it becomes necessary for the controlapparatus to control the network setting memory.

According to a second method, a plurality of sets of setting data thatare stored in the network setting memory are supplied in the firstprocess and a command for selectively loading one set of setting dataout of the plurality of sets of setting data is supplied in the secondprocess. With this method, while it is not necessary to control thenetwork setting memory by the control apparatus, it is necessary toincrease the bus width of the third data transfer means to make itpossible for the processing units to select the sets of setting data.Even when the bus width of the third data transfer means is narrow, ifthere is sufficient memory capacity in the processing units and the timetaken by data transfer is not a problem, a plurality of sets of settingdata and identification information may be transferred in advance to theprocessing unit, with the functions of the processing unit being set bya load command that is supplied in the second process.

In the third method, sets of setting data that are stored in the networksetting memory are supplied in the first process, and the sets ofsetting data in the network setting memory are rewritten by the controlapparatus or the like in another process performed before the firstprocess. With this method, the storage capacity of the network settingmemory can be reduced, though it is necessary to perform a process thatloads sets of setting data in advance into the network setting memory.Also, these first to third methods are not completely different methods,so that it is possible to use a combination of the methods asappropriate. For example, a suitable number of sets of setting data maybe temporarily loaded into a suitable memory in the data processingsystem from an external memory, such as a ROM, a RAM, or a storage disc,which stores a large amount of setting data, with setting data that havebeen selected from this internal memory being supplied to the processingunits. In addition, the bus width of the third data transfer means maybe set so that two or a limited number of sets of setting data can beselected by the processing units, so that setting data that arefrequently required to reconfigure the data paths can be selected merelyusing a command from the second data transfer means.

BRIEF DESCRIPTION OF THE DRAWINGS

FIG. 1 is a block diagram showing the overall construction of anintegrated circuit apparatus to which an embodiment of the presentinvention relates.

FIG. 2 shows the overall construction of an AAP unit.

FIG. 3 shows an overview of a network setting memory.

FIG. 4 shows an example of a data path unit that is suited to processingthat outputs an address.

FIG. 5 shows an example of a data path portion that is suited tooperation processing.

FIG. 6 shows a control unit of an element.

FIG. 7 is a flowchart that shows a control method of the data processingsystem.

FIG. 8 shows an example configuration of a data flow in the matrixportion.

FIG. 9 shows an example configuration of a different data flow in thematrix portion.

BEST MODE FOR CARRYING OUT THE PRESENT INVENTION

The following describes the present invention in more detail withreference to the attached drawings. FIG. 1 shows the overallconstruction of a system LSI 10 according to the present invention. ThisLSI 10 is a data processing system that includes a processor unit 11, anAAP (Adoptive Application Processor) unit 20, an interrupt control unit12, a clock generating unit 13, an FPGA unit 14, and a bus control unit15. The processor unit 11 has a general-purpose construction andperforms general purpose processing, including error handling, based oninstructions that are provided by a program or the like. In the AAP unit20, data flows or virtual data flows that are suited to data processingof special-purpose applications are dynamically configured by aplurality of arithmetic and/or logic elements that are arranged in amatrix. The interrupt control unit 12 controls interrupt handling forinterrupts from the AAP unit 20. The clock generating unit 13 suppliesan operation clock signal to the AAP unit 20. The FPGA unit 14 furtherimproves the flexibility of the operational circuits that can berealized by the LSI 10. The bus control unit 15 controls inputs andoutputs of data to and from the outside. The AAP unit 20 is aconfigurable or reconfigurable unit in which data flows or virtual dataflows that are suited to data processing are dynamically formed.

The AAP unit 20 and the FPGA unit 14 are connected by a data bus 17, sothat data is supplied from the AAP unit 20 to the FPGA unit 14,processing is performed, and the result is then returned to the AAP unit20. Also, the AAP unit 20 is connected to the bus control unit 15 by aninput/output bus 18, and so can exchange data with a data bus on theoutside of the LSI 10. Accordingly, the AAP unit 20 can receive an inputof data from an external DRAM 2 or another device and can output aresult produced by processing this data in the AAP unit 20 back to theexternal device. The basic processor unit (“processor unit” or“processor”) 11 can also input and output data to and from an externaldevice via a data bus 11 a and the bus control unit 15.

The processor 11 and the AAP unit 20 are connected by a data bus 21,which makes it possible to exchange data between the processor 11 andthe AAP unit 20, and an instruction bus 52, which supplies instructionsso that the processor 11 can control the configuration and operation ofthe AAP unit 20. Also, interrupt signals are supplied from the AAP unit20 to the interrupt control unit 12 via a signal line 19, and when theprocessing of the AAP unit 20 has ended or an error has occurred duringsuch processing, the state of the AAP unit 20 can be fed back to theprocessor 11.

FIG. 2 shows an outline of the AAP unit 20. The AAP unit 20 of thepresent embodiment comprises a matrix portion 23 in which a plurality ofprocessing units (hereinafter “elements”) 30 that perform arithmeticand/or logic operations are arranged in a matrix, a network settingmemory 24 that supplies setting data 57 for forming a network to thematrix portion 23, and a save memory 25 for temporarily storing thestate of the network.

The matrix unit or portion 23 includes a plurality of processing units,which is to say, the elements 30, with the elements 30 being arrangedvertically and horizontally in an array or matrix. The matrix unit 23includes first wire sets 51 a and 51 b that connect the elements 30 in anetwork, with these first wire sets 51 a and 51 b being arranged betweenthe elements 30 as a first data transfer means. The wire sets 51 a arerow wire sets that extend in the horizontal direction, while the wiresets 51 b are column wire sets that extend in the vertical direction.The column wire sets 51 b are constructed from a pair of wire sets, 51bx and 51 by, that are disposed on the left and right sides,respectively, of the operation units 30 aligned in the column direction,with these wire sets 51 bx and 51 by being generically referred to asthe “wire sets 51 b” and the actual supplying of data to the respectiveelements 30 being performed from these wire sets 51 bx and 51 by.Switching units 51 c are arranged at the intersections of the wire sets51 a and 51 b, with each switching unit 51 c being able to switch andconnect any of the channels of the row wire set 51 a to any of thechannels of a column wire set 51 b. Each switching unit 51 c includes aconfiguration RAM that stores setting data, with each switching unit 51c fundamentally receiving setting data in the same way as the elements30 that are described below and being controlled by commands suppliedfrom the processor unit 11.

This means that in the matrix unit 23 of the present embodiment, all orsome of the plurality of elements 30 are connected by the wire sets 51 aand 51 b, so that data (the first data) can be routed among the elements30 that are physically arranged apart from one another without consumingclock cycles. Accordingly, it is possible to dynamically configure oneor a plurality of data flows using the plurality of elements 30 toperform the desired processing, with it also being possible todynamically change these data flows with the desired timing.

The matrix portion 23 further includes a second wire set 52 thatsupplies control signals (commands) 55 from the processor unit 11 toeach of the elements 30. In the present embodiment, this wire set 52functions as a second data transfer means. The wire set 52 can transmitcontrol data (the second data) 55 from the processor unit 11 that is thecontrol apparatus to the elements 30 in parallel. To do so, the secondwire set 52 has a function for broadcasting control data 55 from theprocessor unit 11 to the elements 30 in the matrix portion 23. Whendoing so, in the data processing apparatus 10, the processor unit 11transmits the control data 55 having appended the control data with adata flow ID (hereinafter “DFID”) 56 that is information for identifyinga data flow.

The matrix unit 23 further includes a third wire set 53 that connects anetwork setting memory 24 and each of the elements 30 and supplies thesetting data. Accordingly, in the present embodiment the third wire set53 functions a third data transfer means. A two-port RAM is used as thenetwork setting memory 24, with the network setting memory 24 includinga first port 24 a that is connected to the processor unit 11 and asecond port 24 b that is connected to the matrix unit 23. The networksetting memory 24 can be controlled as a memory such as a normal RAM bythe processor unit 11 via the first port 24 a. The second port 24 b isconnected to the third wire set 53, thereby forming a dedicated data busthat connects the network setting memory 24 to each of the elements 30in the matrix unit 23. Accordingly, the network setting memory 24 is amemory with a wide overall bus width.

As shown in the enlargement in FIG. 3, areas 28 that respectivelycorrespond to each of the elements 30 are provided in one bank 24.1 ofthe network setting memory 24. As examples, there is an area (0, 0)corresponding to the element 30 on the 0^(th) row and 0^(th) column andan area (1, 0) corresponding to the element 30 on the 1^(st) row and0^(th) column. These areas 28 may be defined physically, or by addressesin the network setting memory 24. A pair of DFID 58 and setting data (aset of setting data) 57 is stored in each of these areas 28. Thecombination of the DFID 58 and setting data 57 that is stored forcorresponding to each element 30 is supplied to each element 30individually via the third wiring set 53.

The network setting memory 24 includes a plurality of banks numbered24.1 to 24.n, with each of the banks 24.1 to 24.n being assigned adifferent setting number 29 and storing different setting data 57.Accordingly, when a setting number 29 is indicated by the processor unit11 that is the control apparatus of the matrix portion 23, the DFID 58and a set of setting data 57 that correspond to this setting number 29are supplied to each of the elements 30 respectively. According to theDFID 56 and the control data 55 supplied from the second wire set 52,the supplied setting data 57 that is provided individually for eachelement of the plurality of elements 30 is selected and used at the sametime.

The content of the network setting memory 24 can be changed or updatedby loading data, according to control by the processor unit 11, from anexternal memory such as a DRAM 2. When a large number of sets of settingdata 57 can be stored in the network setting memory 24, the networksetting memory 24 does not need to be updated very frequently, which canreduce the overheads of the processing time required by such updating.On the other hand, if only a set of setting data 57 can be stored in thenetwork setting memory 24, the content of the setting data 57 suppliedto the elements 30 can be controlled by only updating the networksetting memory 24.

The matrix unit 23 further includes a fourth wire set 54 that connectseach of the elements 30 to the save memory 25, so that the state of eachelement 30 can be inputted into and outputted from the save memory 25.The save memory 25 in the present embodiment is connected to each of theelements 30 in the matrix portion 23 by the fourth wire set 54 which isdedicated to this purpose. A memory for which a wide bus width can beformed is used, so that the state of each element 30 can be loaded orstored in one clock cycle or an extremely low number of clock cycles. Onthe other hand, if taking several clock cycles for loading and storingthe states of the elements 30 is allowed, a memory with a narrow buswidth can be used by providing a relaying selector.

Each element 30 arranged in the matrix portion 23 includes a pair ofselectors 31 for selecting input data from the pair of column wire sets51 bx and 51 by and an internal data path 32 that performs arithmeticand/or logic operation processing on the selected input data dix and diyand outputs output data do to the row wire set 51 a. It should be notedthat while internal data paths 32 that include a variety of functionsare shown below, such internal data paths are commonly referred to as“internal data path units 32” below. In the matrix portion 23, elements30 that include internal data path units 32 for different processing arearranged mainly in units of rows. In addition, wires for transferringcarry signals are also provided in the wire sets 51 a and 51 b. Thecarry signals can be used as signals that show a carry or as signalsthat show true or false, and in the matrix unit 23, these carry signalsare used for controlling the arithmetic operations and logic operationsof each element 30 and for transferring results to other elements 30.

As examples, the elements 30 that are arranged on the first row at thetop in FIG. 2 have a circuit that is suited to processing that receivesdata from an input buffer of the bus control unit 15. The data pathunits LD for load operations that are arranged in this matrix unit 23receive data from the load bus 18 and output the data to the row wireset 51 a.

The elements 30 arranged on the second and third rows are elements forreading data from the external RAM 2, and are equipped with internaldata path units 32 a that are suited to generating the addressesrequired for loading data.

FIG. 4 shows an example of the data path unit 32 a. This data path unit32 a includes an address generator 38 composed of a counter or the like,and outputs an address as the output signal do. This output signal do issupplied via the row wire set 51 a and column wire set 51 b as it is orafter processing by other elements 30 to the data path unit 32 a as theinput signals dix or diy. The supplied address is selected by a selectorSEL and is outputted via a flip-flop FF from the matrix unit 23 as anaddress for a data input.

These elements 30 include a control unit 60 for controlling the internaldata path unit 32 a, with the control unit 60 setting the functions ofthe internal data path unit 32 a based on the setting data 57 loaded viathe third wire set 53. An initial value or fixed value for the addressgenerating circuit 38, a selection state for the selector SEL, etc., areset according to the setting data 57 in the internal data path unit 32 athat generates an address.

These elements 30 also include a selector 31 for selecting the inputdata from the column wire sets 51 bx and 51 by, with the setting of thisselector 31 also being made by the control unit 60 based on the settingdata 57. The setting of each switching unit 51 c that connects the rowwire set 51 a and the column wire set 51 b is also made by the controlunit 60 of each switching unit 51 c based on the setting data 57. In thematrix portion 23, the elements 30 that are to be connected via the rowwire set 51 a and the column wire set 51 b can be selected according tothe setting data 57, so that data flows can be configured as desired.Also, by changing or selecting the functions of the internal data pathunits 32 according to the setting data 57, it is possible to change theprocess included in each element 30 within the range that can besupported in advance by the internal data path units 32, so that dataflows can be constructed extremely flexibly.

The elements 30 arranged on the fourth and fifth rows include data pathunits (SMA) 32 b that are suited to arithmetic and logic operations. Asshown in FIG. 5, a data path unit 32 b includes a shift circuit “SHIFT”,a mask circuit “MASK”, and an arithmetic logic unit “ALU”. In the sameway as in the other elements, the states of the shift circuit “SHIFT”,the mask circuit “MASK”, and an arithmetic logic unit “ALU” are set bythe control unit 60 based on the setting data 57. Accordingly,operations such as an addition, a subtraction, a comparison, a logicalAND and a logical OR can be performed on the input data dix and diy,with the result being outputted as the output signal do.

Depending on the content of the processing in the matrix unit 23, avariety of elements 30 can be provided. For example, the elements 30arranged on lower row include data path units (DEL) 32 c that are suitedto processing that delays the timing at which data is transferred. Asone example, these data path units 32 c can be composed of a pluralityof selectors and flip-flops FF, with an input signal being outputtedafter being delayed by a desired number of clock cycles. It is alsopossible to provide a data path unit that includes a multiplier or thelike and is suited to multiplication processing, a data path unit thatacts an interface with an FPGA 14 that is provided on the outside of thematrix unit 23, and a data path unit that is suited to generating anaddress for outputting data and others.

As described above, each of these elements 30 has a data path that issuited to special-purpose processing or a special function, such asgenerating an address, with it being possible for the control unit 60 tochange the configuration or function of the element based on the settingdata 57. It is also possible to change the connections to other elements30 in the matrix unit 23 using the first wire sets 51 a and 51 b.Accordingly, in the matrix portion 23 of the present embodiment, each ofthe elements 30 includes a data path or special-purpose circuit that isdedicated to special-purpose processing, so that processing can beperformed at high speed in hardware. At the same time, by changing theconnections between the elements 30 and/or changing the functions of theelements 30 within the limited range, the process performed in thematrix portion 23 are so flexibly changed.

An FPGA is also an architecture where the configuration can be flexiblychanged by changing the connections between transistors, and is anintegrated circuit apparatus where the functions can be freely changedafter the circuit has been manufactured. However, an FPGA does notinclude actual logic gates such as AND gates and OR gates, so that evenif an FPGA can function as a special-purpose operation circuit, the areaefficiency of the FPGA is low, and the operation speed is also notespecially high. Time is taken when the hardware in an FPGA isdynamically changed, and other hardware is required to reduce this time.This means that it is difficult to dynamically control the hardwareduring the execution of an application. FPGAs are not economic, either.

On the other hand, with the data processing apparatus 10 of the presentembodiment that includes the matrix portion 23, a variety of types ofelements that include data paths suited to appropriate orspecial-purpose processing are provided in advance, so that there is noneed to change all the connections between transistors as with an FPGA.This means the hardware can be reconfigured in a short time, and sincethe present architecture does not need to have general-purposeapplicability at the transistor level like an FPGA, the packing densityis improved, making the system compact and economical. In addition,redundant parts of the construction can be omitted, so that theprocessing speed can be increased and favorable AC characteristics canbe achieved.

FIG. 6 shows the control unit 60 of an element 30. This control unit 60includes a decode unit 61, which interprets information such as controlcommands supplied via the second wire set 52, and a configuration RAM62, which stores setting data for the data path unit 32. A DFID 63 andinternal information 64 that includes information of the internalsettings and internal state are stored in the configuration RAM 62. Theinternal information 64 includes, namely, the setting data 57 that issupplied via the third wire set 53 and information that can trace theprocessing in the data path unit 32, such as an operation status of thedata path unit 32. The setting data 57, as examples, includes controlinformation on operation units in the data path unit 32, parameters suchas initial values and fixed values, selection information on a path inthe data path unit, and wiring between elements (which is to sayselection information for the first row wire sets 51 a and 51 b). Theconfiguration RAM 62 can be any rewritable memory and so may be aregister, EEPROM, etc.

The decode unit 61 includes: a selector 65, a comparator 66 and acommand decoder 67. The selector 65 selects one of a DFID 58 that issupplied from the third wire set 53, a DFID 63 that has already beensupplied from the third wire set 53 and is stored in the configurationRAM 62, and a DFID 71 that is supplied from the save memory 25 that isdescribed later. The comparator 66 compares the DFID selected by theselector 65 and the DFID 56 supplied from the second wire set 52. Thecommand decoder 67 decodes and executes the control information(command) 55 supplied from the second wire set 52 when the comparator 66finds that the DFIDs match.

FIG. 7 shows an overview of the processing in the data processing system10 that sets and controls data flows in the matrix portion 23 throughthe processing of the processor 11 and the processing of the controlunits 60 of the elements 30. The control method of the data processingsystem 10 for data flows includes a first process 101 that supplies theDFID 58 and the setting data 57 via the third wire set 53 and a secondprocess 102 that supplies the DFID 56 and the command 55 via the secondwire set 52.

In step 109, the processor 11 fetches an instruction from a program 11 pstored in a code RAM 11 c, and in step 110, when the fetched instructionis an instruction for controlling the configuration of data flows in thematrix portion 23, the processor 11 executes the first process 101 andthe second process 102. When the fetched instruction is an instructionthat controls data flows that have already been configured, theprocessor 11 executes the second process 102. In the first process 101,when the processor 11 judges, based on the program 11 p, in step 111that it is necessary to supply new setting data 57, in step 114 theprocessor 11 supplies the DFID 58 and the setting data 57 from thenetwork setting memory 24 to each of the elements 30 individually viathe third wire set 53. At this point, when it is necessary to update thecontent of the network setting memory 24 (step 112), the processor 11reads setting data 57 that is stored in the DRAM 2, etc., and updatesthe network setting memory 24 (step 113). This rewriting of the networksetting memory 24 can be performed in units of banks, in units ofsetting numbers, or the entire contents of the network setting memory 24are also be able to be updated.

In step 114, there are a number of methods for supplying differentsetting data 57 via the third wire set 53 to the intended elements 30.In a first method, in step 114, a set of setting data 57 that is to beloaded into an element 30 is selected out of the plurality of sets ofsetting data 57 that stored in the network setting memory 24 for thatelement and is outputted, with this set of setting data 57 being loadedin the second process 102 below. When there is little capacity in thenetwork setting memory 24, such as when only one setting number can bestored, a set of setting data that has been updated in step 113 issupplied to the element 30. This corresponds to a third of the methodsmentioned above.

In the second method, in step 114, a plurality of sets of setting data57 that are stored in the network setting memory 24 for each elementsare supplied in a state that enables the element 30 to select one set ofsetting data 57, and in the second process 102, the element 30 selectsand loads the one set of setting data 57 from the plurality of sets ofsetting data 57 based on a command. With this second method, theoperation of the network setting memory 24 by the processor 11 isreduced, which reduces the works of the processor 11, though the buswidth of the third wire set 53 needs to be increased. It is alsopossible to have a plurality of combinations of setting data 57 andidentification information 58 downloaded in advance into theconfiguration RAM 62, etc., of the control unit 60 in the elements 30,though this makes it necessary to provide sufficient memory capacity inthe elements 30 and to provide sufficient time for transferring thedata.

It is also possible to use a control method that is a combination ofthese methods. As one example, using the bus width of the third wire set53 that can limited number of sets of setting data 57 such as two setsare selectable by an element 30, so that setting data that is oftenrequired when reconfiguring the data paths can be selected using just acommand received via the second wire set 52.

In the second process 102, in step 115 the processor 11 supplies, basedon the program 11 p, the DFID 56 and the command 55 via the second wireset 52 to every element 30 in the matrix unit 23. In step 116, thecontrol unit 60 of each element 30 receives the DFID 56 and the command55 via the second wire set 52, and then in step 117, the control unit 60selects the DFIDs that are to be compared with the DFID 56 supplied viathe second wire set 52, which is to say, the control unit 60 selects aDFID that this processing unit 30 will belong to. In the presentembodiment, as described above the selector 65 can select one of theDFID 58 supplied via the third wire set 53, the DFID 63 stored in thecontrol unit 60, and the DFID 71 stored in the save memory 25. In step118, when the selected DFID matches the DFID 56 supplied via the secondwire set 52, the command 55 is executed in step 119.

In the data processing apparatus 10, when an instruction Ins1, whichindicates an execution of a process that composes data flows with theDFIDs 1, 2, and 3 in the matrix portion 23 using the setting data storedwith the setting number 1 in the network setting memory 24, is presentin the program 11 p stored in the code RAM 11 c of the processor 11, instep 114, the processor 11 outputs a control signal φ1 for selecting thebank 24.1 in the network setting memory 24. In addition, in step 115 theprocessor supplies a start command 55 a for forming the data flows tothe elements 30 via the second wire set 52. One example of the startcommand 55 a is shown below.start DFID, OP  (1)

When, in step 118, the DFID 56 supplied together with the commandmatches the DFID selected by the selector 65, in step 119 the decoder 67of the control unit 60 in the element 30 interprets and executes thestart command 55 a. In the present embodiment, a control signal forstoring the setting data 57 supplied from the third wire set 53 isoutputted to the configuration RAM 62. Here, as described above, aplurality of DFIDs or a single DFID can be issued together with thecommand 55.

The “OP” part of the start command 55 a is composed of parameters foroptions. One parameter is information for selecting a setting number.When the bus width of the third wire set 53 is wide and sets of settingdata 57 of a plurality of banks in the network setting memory 24, whichis to say, sets of setting data 57 with a plurality of setting numbersis provided via the third wire set 53, a set of setting data with one ofthese setting numbers can be stored in the configuration RAM 62 by thisparameter. Accordingly, the processor 11 does not need to select a setof setting data that is to be outputted from the network setting memory24 or the processor 11 shall only make a selection of setting data inlarger units, such as units of block. This makes it easy to control thenetwork setting memory 24 and raises the processing speed. However,since it is necessary to provide sufficient bus width for the third wireset 53, the data processing apparatus 10 becomes larger.

The state of the selector 65 that is set in step 117 may be defined bythe setting data 57 stored in the configuration RAM 62, or a command 55that sets the state of the selector 65 may be supplied via the secondwire set 52. It is also possible for the decoder 67 to decode thecommand 55 in advance and for the state of the selector 65 to be set bythe command itself or by parameters that are appended to the command. Ineither case, the result of the decoding is executed only when the DFIDselected by the selector 65 and the DFID 56 match.

When in step 117, the selector 65 selects the DFID 58 which has beensupplied with the setting data 57 via the third wire set 53, the settingdata 57 is updated in the elements 30 where this DFID 58 matches theDFID 56 indicated by the start command 55 a. Accordingly, the DFID 56which has been supplied with the start command 55 a is the DFID thatshows the data flow that is to be newly configured in the matrix unit23.

On the other hand, it is also possible for the selector 65 to select theDFID 63 that is stored in the configuration RAM 62, which is to say, theDFID that identifies the data flow to which the element 30 currentlybelongs. In this case, the DFID 56 that is supplied together with thestart command 55 a is the DFID that indicates the data flow to beupdated in the matrix portion 23.

In either case, the setting data 57 that is supplied to the plurality ofelements 30 from the network setting memory 24 via the third wire set 53can be synchronously set by the start command 55 a in a plurality ofelements 30 identified by the DFID 56 supplied with the command.Accordingly, there is no need to supply setting data to each element oneby one, so that a new data flow can be configured at high speed, forexample, in one clock cycle. In addition, the DFIDs that are used forthese purposes do not need to include any information that identifieseach element 30, so that as shown in the present embodiment, extremelysimple data with a small data amount is sufficient. This makes itpossible to provide a data processing apparatus 10 that can change thedata flow extremely easily and at high speed.

In the data processing system 10, the address regions 28 of the networksetting memory 24 that respectively correspond to the elements 30 areseparately and directly connected to the control units 60 of eachelement 30 by the third wire set 53. Accordingly, if the bus width ofthe third wire set 53 is sufficient and the operation frequency issufficiently high for delays caused by distance to be negligible, it ispossible to use the address regions 28 in the network setting memory 24that correspond to each element 30 as the configuration RAMs 62 withouthaving to load the setting data 57 of the network setting memory 24 intothe configuration RAM 62 in the control unit 60 of each element 30.

The following describes a number of example commands that use DFIDs inthe data processing apparatus 10 of the present embodiment. First a haltcommand 55 b that halts the operation of a data flow is as follows.freeze DFID  (2)

When attempting to change the data flow without halting the operation ofthe data flow, there is the possibility of erroneous operations beingmade during the switching or after the switching. As one example, whenhardware resources that were performing memory accesses in each clockcycle before changing over are operational during the changing, accessends up being made to unexpected addresses. Even if such access does notcause a fatal error, external bus cycles are generated, resulting in atleast a lowering of performance. There is also the possibility that whenthe data flow of the matrix unit 23 is dynamically switched, it may notbe possible to reproduce the data flow. For example, when data flows areswitched without stopping the data flows, the data flows end upoperating even during the switch. If this happens, the next time thesetting data is restored, the data flow is reproduced, and theprocessing is resumed, there are cases where a different result isobtained to when the data flow is not switched. This is to say, theinternal information that is set back in each element that composes thedata flow in order to reproduce the data flow can end up including bothvalues from before the switch and values that have been rewritten duringthe switch.

Accordingly, if an instruction Ins2 for switching or changing the dataflow is present in the program 11 p, in step 115 the processor 11issues, via the second wire set 52, a halt command (freeze command) 55 bthat indicates the intended data flow using a DFID and has the operationof this data flow halted. When the control unit 60 of an element 30receives a freeze instruction 55 b with a matching DFID, the operationof the element 30 is stopped. In addition to stopping the functioning ofthe data flow, this freeze instruction 55 b may have a function forhaving the data flow restart the operation when the data flow istemporary stopping the functioning. In the data processing apparatus 10of the present embodiment, information that identifies the data flows towhich the elements 30 belongs is assigned in advance as DFIDs, so thatby issuing a DFID together with a halt command 55 b, there is no need togenerate addresses if referring from the inside of elements.

By providing this kind of halt command 55 b, a data flow that is on orunder operation can be indicated and the functioning of this data flowcan be stopped, thereby suppressing unnecessary bus accesses. Also, whenthe data flow is dynamically changed, the reproducibility of the dataflow is ensured. Accordingly, this control method where DFID informationthat identifies a data flow is appended and the halt command 55 b issupplied via the second wire set 52 so that the data flow is stopped andthen operated is effective not just in a data processing system whereelements are assigned DFIDs for each data flow via the third wire set 53as in the present embodiment but also in a data processing apparatuswhere DFIDs are appended via a network, such as the first wire sets 51 aand 51 b in the present embodiment.

For a data flow is dynamically reconfigured, the store command 55 c andload command 55 d that have the data flow that is currently operatingtemporarily saved and then reactivated are as follows respectively.Storev DFIDLoadv DFID  (3)

When a number of processes are to be executed by the matrix portion 23,it is possible to perform a following process after first waiting forthe processing that currently occupies the elements 30 in the matrixportion 23 to end. However, such control method is not suitable when theprocessing that is required is a high-priority process where real-timeresponse is required. In the matrix portion 23, when elements that arecoincidently not in use at the configuration can be collected to realizethe next process, the configuration cannot proceed if the sufficientelements 30 are not available. Also, in a method where elements 30 thatare available are collectively used, it is not possible to predict inadvance which elements 30 will be available, so that the wiring methodfor wiring resources that connect the available elements 30, which is tosay the arrangements of first row wire sets 51 a and 51 b, has to becalculated each time, which is time-consuming. This is also not suitedto cases where real-time processing is required.

There is also a method where the processing that is currently beingperformed is interrupted, the other processing with high priority isexecuted, and the interrupted processing is recommenced from thebeginning once the high-priority processing has ended. However, there isa clear waste of processing time in this case, and this method cannot beused when it is not possible to repeat the processing that has beeninterrupted.

On the other hand, in the data processing system 10, when an instructionIns3 for executing a process with high priority is present in theprogram 11 p, in step 115 the processor unit 11 issues a store command55 c with a DFID showing the data flow with the high priority. After theinternal information 64 of the elements 30 that belong to this data flowhas been stored in the save memory 25, the desired elements 30 arereleased. Next, based on the program 11 p, in step 115 the processorunit 11 issues the start command 55 a, so that the data flow forexecuting the high-priority processing can be configured and thisprocessing can be performed. After this, in step 115, the processor unit11 issues a load command 55 d with the DFID for the data flow to bereproduced, so that the internal information 64 is loaded from the savememory 25, the saved data flow is reconfigured, and the processing canbe resumed.

Accordingly, when high-priority processing is required, such asprocessing that needs to be performed in real-time, such processing canbe given priority and executed by the matrix unit 23. When thishigh-priority processing ends, the suspended data flow is reconfigured,the suspended state is reproduced, and the processing can be resumedfrom the suspended state. By doing so, processing time is not wasted.

This means that when a store command 55 c has been issued, in eachcontrol unit 60 of the elements 30, the DFID 58 supplied via the thirdwire set 53 is compared with the DFID 56 supplied via the second wireset 52 with the command 55 c, and when these DFIDs match, in step 119the processing is halted and the internal information 64 and the DFID63, both in the configuration RAM 62, are stored in the save memory 25via the fourth wire set 54. If sufficient time is available for writingsuch data, a parallel-serial conversion may be performed by a transfercircuit 75 that is composed of a selector and a switching circuit, whichmakes it possible to reduce the bus width of the wire sets and to reducethe bus width of the interface of the save memory 25.

Also, if it is possible to provide sufficient capacity in theconfiguration RAM 62 of the control unit 60 in each element 30 forstoring the internal information and DFID to be saved, it is alsopossible to use the configuration RAM 62 as the save memory. In thiscase, if the internal information 64 is written in a mirror state in thebit region used as the save memory or register while the element 30 isin usual processing, processing for saving the internal information 64according to a store instruction 55 c becomes unnecessary.

While the functioning of a data flow is described as being haltedaccording to a store instruction 55 c, the functioning of the data flowcan be stopped in advance by issuing a freeze instruction 55 b beforethe store instruction 55 c. When an array of the elements 30 that arerequired to configure the data flow to be processed with priority doesnot match the array of elements 30 that configure the data flow to besaved, a store instruction 55 c or a freeze instruction 55 b thatindicates the DFID or DFIDs of the data flows to be saved shouldpreferably be issued. In this case, by comparing this DFID with the DFID63 stored in the configuration RAM 62 of each element 30, the internalinformation 64 of the suitable elements 30 can be saved.

When the DFID 56 of the data flow to be restored is issued together witha load command 55 d, in step 118 the control unit 60 of each element 30compares the DFID 56 with the DFID 71 stored in an address region 73,which corresponds to the each element 30, in the save memory 25. Whenthese DFIDs match, in step 119, the internal information (conditiondata) 72 that has been saved in the save memory 25 is loaded into theconfiguration RAM 62. When the internal information 64 of every element30 that composes the data flow with the indicated DFID 56 has beenrestored, the processing that was suspended is resumed.

In this control method, data flows are dynamically reconfigured bytemporarily saving the data flows that are operational and beingre-operational the data flows by supplying, via the second wire set 52,the store command 55 c and load command 55 d together with the DFIDinformation for identifying the data flows as described above, thoughthis control method is not limited to a data processing system whereDFIDs are assigned to elements for each data flow via the third wire set53 as in the present embodiment. As one example, this control method isalso effective in a data processing system where DFIDs are assigned viathe first wire sets 51 a and 51 b that compose the network.

FIG. 8 shows a state where a command φ1 that indicates the settingnumber [1] for the network setting memory 24 is issued from theprocessor 11, and a start command 55 a with identifications [1,2,3] asthe DFIDs 56 is issued via the second wire set 52 to the matrix portion23. In each element 30, sets of setting data 57 with the DFID 58 [1],[2], or [3] is supplied from the network setting memory 24 by the thirdwire set 53 to the corresponding configuration RAMs 62 of elements 30and the set of setting data 57 is latched or stored respectively. Thesecond wire set 52 and the third wire set 53 are also connected to theswitching units 51 c that belong to the first wire sets, if necessary,connection information for the first wire sets 51 a and 51 b also beingprovided. With this construction, after a start command 55 a has beenissued, elements 30 are connected by the first wire sets 51 a and 51 bin a short time, such as one clock cycle, a data flow 81 with the DFID[1], a data flow 82 with the DFID [2], and a data flow 83 with the DFID[3] are configured, and processing is commenced.

Next, when a freeze command 55 b is issued from the processor 11 withidentifications [1,2] as the DFIDs 56, the operations of the elements 30that belong to the corresponding data flows 81 and 82 are halted,thereby suspending the processing in the data flows 81 and 82. However,the processing by the elements 30 that belong to the data flow 83 thatis not indicated by the DFIDs 56 is continued.

After this, the command φ1 that indicates the setting number [2] for thenetwork setting memory 24 is issued from the processor 11, and a storecommand 55 c with indications [4,5] as the DFIDs 56 is issued to thematrix portion 23 from the processor 11. Based on the DFIDs 58 that aresupplied from the third wire set 53, the internal information of theelements 30 required for constructing a data flow, which is to say, theelements 30 that configured the current data flows 81 and 82, are storedin the save memory 25 via the fourth wire set 54. If necessary, thestates of the switching units 51 c that belong to the first wiring setare also stored in the save memory 25. The sets of setting data 57 withthe DFIDs 58 [4] and [5] that are supplied from the network settingmemory 24 via the third wire set 53 are stored in the correspondingconfiguration RAMs 62 of elements 30 respectively. In this way, as shownin FIG. 9, a data flow 84 with the DFID [4] and a data flow 85 with theDFID [5] are configured and processing is commenced.

Accordingly, after the store command 55 c has been issued, theconfiguration of the matrix portion 23 is switched or changed within afew clock cycles and processing commences according to the new dataflows. During this time, the processing by the data flow 83 continueswithout being suspended.

Once the processing in the data flows 84 and 85 end, a load command 55 dwith indications [1,2] as the DFIDs 56 is issued from the processor 11to the matrix portion 23. This load command 55 d has the internalinformation 72 of the elements 30 corresponding to the DFID 71 that weresaved in the save memory 25 stored in the configuration RAMs 62 via thefourth wire set 54 and, as shown in FIG. 8, has the data flows 81 and 82reconfigured. The internal states of the elements 30 belonging to eachof the data flows 81 and 82 are restored to the same states as when theprocessing were suspended, so that by commencing processing according tothese data flows 81 and 82, the processing can be resumed from the pointwhere the processing were suspended.

In this way, in the data processing apparatus 10 of the presentembodiment, a plurality of functions can be easily realized by thematrix portion 23 in which the plurality of elements 30 can be connectedin a network by the first wire set 51. It is possible to have elements,i.e., the devices composing the network, selectively operate by merelyinvestigating whether the DFIDs to be assigned to the elements 30indicate that execution is possible. Accordingly, it is easy for theprocessor 11 or another control apparatus on the outside of the matrixunit 23 to request the elements 30 in the matrix unit 23 to performprocessing. That is, when there is a request from outside for a certainfunction, or a data flow, in the network, it is sufficient to indicate aDFID that is identification information for that function.

It is also possible to provide a program or program product 11 p thatincludes instructions for executing processing that has the processor 11issue the type of commands described above in order to change theconfiguration of the network (data flows) of the matrix unit 23 and tocontrol the data flows. By changing the content or order of theinstructions in the program 11 p, it is possible to change theprocessing executed by the data processing apparatus 10, which isrealized as a system LSI or the like, from the hardware configurationstage. It is also possible to change the processing executed by the dataprocessing apparatus 10 from the hardware configuration stage byreplacing the content or context of the network setting memory 24.Accordingly, the present invention can provide a data processing systemthat can execute processing of different data flows and different datapaths at the processing execution stage even though the sameconstruction is provided as the hardware resources.

The method for using the DFIDs is not limited to that described above.As one example, the DFID [0] can be used to indicate every element 30,so that a command can be supplied to every element 30 and the settingdata in all of the elements 30 can be updated without affecting theDFIDs 58 supplied from the third wire set 53 and the DFIDs 63 storedinternally. The DFID [-1] can be used to indicate data that is unrelatedto the elements 30 and the second wire set 52 can be used other controlthat is unrelated to the control of the elements.

In addition, the data provided from the second wire set 52 is notlimited to control commands. The data flows constructed from elementsarranged in a network often repeat the same type of operations, thoughthe coefficients of such operations are changed often. Accordingly, inthe present system 10, the coefficients can be changed according to datasupplied from the second wire set 52 without changing the content of thenetwork setting memory 24, which is to say, without changing the settingdata 57. The setting data 57 of the network setting memory 24 can alsobe reused with only the parts that need to be changed being amended bythe processor 11, so that by supplying a start command 55 a from thesecond wire set 52, the setting data 57 can be set in the elements 30any number of times.

Like an ordinary memory, the network setting memory 24 may also bedirectly rewritable for the processor unit 11 that is the controlapparatus. This allows great freedom to programmers. If such a memory ishidden in each element and cannot be directly rewritten by the processorunit 11, another method shall be used where other identificationinformation that identifies each element individually, such as anaddress, is provided to each element separately together with thesetting information. Such another method requires repeat of the sameoperation a number of times equal to the number of elements that composea data flow, which makes this extremely time-consuming. The circuitsalso operate inefficiently, which increases power consumption. While itis possible to use more another method where the elements are connectedin a tree pattern, and an address showing a desired element is insertedtogether with the setting information into the roots of the tree, thisalso takes time and makes a partial amendment of the data flowsdifficult.

The network setting memory 24 of the present embodiment is connecteddirectly to each element 30 by the third wire set 53 that has a wideoverall bus width. This means that the settings can be made at highspeed in one clock cycle. Control requests (suspend, resume) and DFIDsidentifying the control targets are transferred or broadcast to theelements 30 by the second wire set 52, which such control also beingperformed in one clock cycle.

In addition, the setting data 57 that is stored in the network settingmemory 24 may be generated at any time by the processor 11. It is alsopossible for part of sets of the setting data that has been prepared inadvance and stored in the external DRAM 2 or the like to be downloadedinto the network setting memory 24 by the processor unit 11 and thenused.

While the arrangement of the wire sets described above are exemplaryshown, the present invention is not limited to such description. It issufficient for the first wire sets 51 a and 51 b that function as thefirst data transfer means to be wires or a data transfer means that canbe flexibly routed between elements. As one example, by increasing thenumber of input selectors, or by increasing the number of inputs, eachappliance can be made capable of more complicated operations. Morecomplicated operations are also possible by increasing the number ofoutput selectors, or the number of outputs. In addition, there is noneed for the output selectors and outputs to be connected in aone-to-one fashion, and one output may be connected to a plurality ofselectors or a plurality of outputs may be connected to one selector.The network may be constructed, if time consuming for communicationbetween elements is sufficient, data can be sent and received byindicating the addresses of elements.

The second wire set 52 that functions as the second data transfer meansmay be provided with an appropriate number of signal lines for thepossible types of DFID, with such signal lines being used to show thedifferent DFIDs. Such modification can also be applied for the thirdwire set 53.

The data processing apparatus 10 described above is an example where thepresent invention is embodied in a processor apparatus or LSI apparatuswhere the elements 30 are mounted on a semiconductor substrate.Accordingly, the present invention can provide an LSI or an ASIC thatcan perform real-time processing with favorable AC characteristics,where data flows that are suited to the processing of an application canbe dynamically reconfigured and hardware resources can be used with thegreatest possible efficiency.

The LSI apparatus 10 of the present embodiment is also characterized inthat by changing the program 11 p and/or the setting data 57, it ispossible to put an LSI with the same hardware resources to a pluralityof uses and applications. The program 11 p and/or the setting data 57can be provided separately to the data processing apparatus by storingthe program and/or setting data in a suitable recording medium, such asa ROM that can be distributed independently, or can be provided via acommunication means such as a computer network. This means that bychanging or updating the program 11 p and/or the setting data 57, it ispossible to improve the processing performance of and add new functionsto an LSI or an information processing terminal or the like in whichsuch an LSI is used. This means that the functions of an LSI that areessentially fixed at the end of the development stage can be changed inthe same way as a firmware upgrading, which greatly reduces the burdenof manufacturers during design and manufacturing and makes it possibleto provide users with an LSI apparatus that can always be used in anoptimal condition.

Also, according to the present invention, the plurality of processingunits (the “elements” in the example described above) that are connectedby a network to realize a given function can be different semiconductorapparatuses, different circuit boards, or even devices that are remotelyprovided. In the data flows in the present invention, the followingfunctions can also be realized. First, some or all of the devices thatcan be connected in a network are used to form a data flow, data ispassed over in or along this data flow and processed, with the devicesat the respective ends of the data flow receiving the data from outsidethe network and outputting the processed data out of the network. Theparts composing this data flow are autonomously or heteronomouslycontrolled, so that as one example control is performed to temporarilystop the entire operation of the data flow if there is a blockage at theoutput side. Also, data flows do not actively exchange informationbetween one another during the processing and are fundamentallyprocedures that operate independently of one another.

As described above, with the present invention, processing (setting,control and execution) can be easily realized for such “functions”. The“setting” stage defines a “function” by selecting devices that composethe “function” and assigning roles to each of the devices. A request forsuch setting can be issued from outside the “function”. The “control”for a “function” is starting and stopping of the operation of the“function”, and controlling can be issued from outside the “function”.

The “execution” refers to the autonomous operation of the “function”,and includes synchronization control and the like that occurs during theoperation of the “function”. Such “execution” is thought to include thefollowing. First is the synchronization of input data. When operationsare performed by an ordinary device, usually, there are two or more setsof input data. In such cases, all of the input data should preferably beinputted into the devices simultaneously. If the inputs into a networkare associated with the “function”, when the inputs are received intothe network, flow control of input data can easily synchronize aplurality of sets of input data and inputs them into the “function”.Second is flow control over output data. When there is a blockage foroutputs from the network (a buffer apparatus is provided in many casesfor the output of the network, and such blockages correspond to when thebuffer apparatus is full), should the “function” continue to outputdata, the output data will simply be lost. However, if the output of thenetwork is associated to the “function”, the network can indicateblockage to the “function” and the “function” can therefore autonomouslystop operating until outputting becomes possible once again. The presentinvention makes it possible to perform centralized management usingidentification information (DFIDs) that indicate “functions” withouteliminating the possibility of having centralized control performed by acontrol apparatus in the network. This means that if the abovephenomenon (i.e., a blockage) is detected by a monitoring apparatus, itis possible to instruct each “function” to temporarily stop and thenresume operations.

The above is different to the identification method used in conventionalsystems where devices are arranged and operated in a network, and inparticular differs from an LSI architecture. Each of the devicescomposing the network is assigned fixed or dynamic identificationinformation (an ID or address). However, when a network is constructedbetween devices and data is transferred, the assigning of fixed ordynamic IDs that one-to-one correspond to the devices produces onlyredundant information in cases where the devices that are to operate canbe specified using the physical positions of such devices. In addition,in cases when a plurality of “functions” are present in the network,assigning separate IDs to each devices does not facilitate the operationfor one of such “functions”. An operation that has each of the devicesoperate by indicating each device individually is clearly redundant,with wiring and processing time being wastefully used for indicatingdevices.

By combining all of the devices to realize a single “function”, itbecomes possible to eradicate the need to identify devices for control,though since a plurality of “functions” cannot be performedsimultaneously, such method makes wasteful use of hardware resources.While it is possible to regard different IDs as the same according tocertain special rules, such as by using a method where some of the IDsof the devices are masked to leave others, this is merely a compromisefor the problem of the inability to supply different settings forindividual devices from outside without individually indicating the IDsof the devices, so that the fundamental problem remains. This means thatIDs have to be wastefully assigned to each device, which reduces theclarity and flexibility of programming. Also, there is still the problemof having to access each of the devices one by one in order to makedifferent settings in each device, so that the functions cannot bedynamically switched in a short time.

On the other hand, with the present invention, by introducing a thirddata transfer means that multiply distribute setting data to individualdevices and assigning identification information to the “functions”themselves that are dynamically defined in a network, the redundancydescribed above can be eradicated, programming is made easier, and asimple construction that is sufficient for the setting, control, andoperation of “functions” is realized.

INDUSTRIAL APPLICABILITY

The data processing system and control method of the present inventioncan provide as system that is capable of a variety of data processingsuch as a system LSI and ASIC. The data processing system of the presentinvention is not limited to electronic circuits, and can also be adoptedin a data processing apparatus that is based on optical circuits oroptical-electronic circuits. The data processing system of the presentinvention can execute data processing at high speed using reconfigurablehardware, and so is suited to a data processing apparatus for high-speedand real-time processing, such as network processing and imageprocessing.

1. A data processing system, comprising: a plurality of processingunits; first data transfer circuits for connecting the plurality ofprocessing units in a network, exchanging first data, and configuring atleast one reconfigurable data flow by connecting at least two of theplurality of processing units; second data transfer circuits that aredifferent from the first data transfer circuits for supplying,independently of the first data transfer circuits, second data to eachof the plurality of processing units in parallel from a controlapparatus; and third data transfer circuits that are different from thefirst and second data transfer circuits, for supplying, independently ofthe first and second data transfer circuits, setting data to each of theplurality of processing units individually from a network settingmemory, the setting data being data for setting a data flow,corresponding to a function, by changing a set of connections betweenprocessing units of the plurality of processing units connected with thefirst data transfer circuits, or by changing a process included in theprocessing units, wherein the network setting memory stores sets ofsetting data and identification information for each of the plurality ofprocessing units, the identification information identifying theprocessing units connected by the first data transfer circuits forconfiguring a particular data flow, the third data transfer circuitssupplying the identification information together with the setting data,wherein the control apparatus issues control information with theidentification information as the second data for controlling operationof the processing units, and wherein each of the plurality of processingunits includes a control unit that operates based on the second data,wherein the second data is selected based on the identificationinformation supplied via the third data transfer circuits.
 2. A dataprocessing system according to claim 1, wherein each of the plurality ofprocessing units includes a memory for storing the identificationinformation.
 3. A data processing system according to claim 1, whereinthe control unit is adapted to load the setting data according to thesecond data.
 4. A data processing system according to claim 1, whereinthe control unit is adapted to start or stop operation according to thesecond data selected.
 5. A data processing system according to claim 1,wherein the control unit is adapted to store, in a save memory, internalinformation on the processing unit when stopping an operation accordingto the second data and commencing another operation after anotherinternal information saved in the save memory has been loaded.
 6. A dataprocessing system according to claim 5, wherein the saving means storesthe identification information together with the internal information inthe save memory.
 7. A data processing system according to claim 1,wherein the processing unit further includes a plurality of selectableinternal data paths, and the setting data includes data for selectingthe internal data paths.
 8. A data processing system according to claim1, wherein the network setting memory stores a plurality of sets ofsetting data for each of the plurality of processing units, and thecontrol apparatus selects the set of setting data, from the pluralitysets of setting data, that is to be set synchronously with at least partof the plurality of processing units, has the selected set of settingdata outputted from the network setting memory, and issues, as thecontrol information, a command for loading setting data.
 9. A dataprocessing system according to claim 1, wherein the network settingmemory stores a plurality of sets of setting data for each of theplurality of processing units, and the control apparatus issues, as thecontrol information, a command for selecting the set of setting datafrom the plurality of sets of setting data in the network setting memoryand loading setting data.
 10. A data processing system according toclaim 1, wherein the control apparatus changes the plurality of sets ofsetting data in the network setting memory.
 11. A data processing systemaccording to claim 1, wherein the circuit board is a semiconductorsubstrate.
 12. A control method for a data processing system, whereinthe data processing system includes a plurality of processing units,first data transfer circuits for connecting the plurality of processingunits in a network, exchanging first data, and configuring at least onereconfigurable data flow by connecting at least two of the plurality ofprocessing units, second data transfer circuits that are different fromthe first data transfer circuits for supplying, independently of thefirst data transfer circuits, second data to the plurality of processingunits in parallel from a control apparatus, and third data transfercircuits that are different from the first and second data transfercircuits, for supplying, independently of the first and second datatransfer circuits, setting data to each of the plurality of processingunits individually from a network setting memory, the setting data beingdata for setting a data flow, corresponding to a function, by changing aset of connections between processing units of the plurality ofprocessing units connected with the first data transfer circuits or bychanging a process included in the processing units, wherein the networksetting memory stores sets of setting data and identificationinformation for each of the plurality of processing units, theidentification information identifying the processing units connected bythe first data transfer circuits for configuring the data flow, thecontrol method comprising: supplying, via the third data transfercircuits, the identification information and together with the settingdata; and issuing, from the control apparatus, control information withthe identification information as the second data via the second datatransfer circuits, and operating a control unit included in each of theplurality of processing units according to the second data selected,based on the identification information that is supplied via the thirddata transfer circuits or the identification information that has beenpreviously supplied.
 13. A control method according to claim 12, whereinthe control information includes a first command for loading the settingdata into the processing unit.
 14. A control method according to claim12, wherein the control information includes a second command forstarting or stopping operation of the processing unit.
 15. A controlmethod according to claim 12, wherein the control information includes athird command for stopping processing of the processing unit and storinginternal information on the processing unit in a save memory and afourth command for loading the internal information stored in the savememory and starting the processing of the processing unit.
 16. A controlmethod according to claim 15, wherein the internal information is storedtogether with the identification information in the save memory by thethird command and the fourth command is selected based on theidentification information stored in the save memory.
 17. A controlmethod according to claim 12, wherein the network setting memory storesa plurality of sets of setting data for each of the plurality ofprocessing units, out of the plurality of sets of setting data that arestored in the network setting memory, a set of setting data to be setsynchronously with at least part of the plurality of processing units issupplied, and the control information includes a command for loading theset of setting data.
 18. A control method according to claim 12, whereinthe network setting memory stores a plurality of sets of setting datafor each of the plurality of processing unit, the plurality of sets ofsetting data are supplied, and the control information includes acommand for selecting and loading a set of setting data out of theplurality of sets of setting data.
 19. A control method according toclaim 12, wherein the network setting memory stores a set of settingdata being respectively corresponding to each of the plurality ofprocessing unit, is supplied, and the control method further includesrewriting the set of setting data in the network setting memory.